1. Field of the Invention
This invention relates generally to analog to digital converters, and more particularly to an analog to digital converter having a high speed sampling rate utilizing a sample and hold circuit for each bit resolution that allows the circuit for the most significant bit to start a new conversion at each clock pulse.
2. DESCRIPTION OF THE PRIOR ART
The successive approximation encoding technique is widely used today and is the fastest conventional time serial logic known. More encoders of this type are used in multiplexed analog to digital data systems than in any other kind. These converters compare the analog output of a digital to analog reference converter to an unknown input voltage. Simple digital logic perform the sequential steps.
Starting with the most significant bit, the weight of each binary reference bit is fed to the D/A voltage summer and the output of the D/A is compared against the unknown input voltage. If the D/A output is less than the unknown voltage, the bit is turned off, but if the output is greater than the unknown voltage, then the bit is turned on. This continues until all the reference bits have been compared against the unknown voltage. At the end of the series of bit weight tries, a voltage sum is attained which equals the unknown input analog voltage with an accuracy of .+-. one half the least significant bit weight. Most successive approximation encoders are closed-loop analog to digital servos consisting of three main elements:
A D/A converter (either resistive, capacitive, or inductive); ladder; an amplifier to detect the difference between input analog voltage and the converter output; and a digital servo.
The comparison amplifier and the D/A converter are the components which introduce errors in A/D conversion. The comparison amplifier is limited in its slew rate. Thus the total A/D speed of conversion time is limited by the slew rate of the comparison amplifier and the D/A conversion rates. It is desirable to increase the conversion rate of analog-to-digital converters to accommodate high frequency signals.
To increase speed, a new analog-to-digital converter technique called a time parallel encoder or flash converter has been developed. The basic principal of the time parallel encoder is quite simple. There is a reference voltage provided for each and every binary value, and detection circuitry for each reference voltage to determine if the unknown analog voltage V.sub.x is within one half a binary increment of each voltage. Since the decisions are essentially in parallel, only one amplifier delay time is required for the binary number decision. The main advantage of these encoders is speed. For example, a four bit ten-ns parallel encoder at a 100 MHz rate is commonly available. The main drawback of these encoders is the large amount of hardware they require for more than three binary bits, although integrated circuits are are easing this problem somewhat.
For an example, in a four significant binary bit encoder, time parallel encoders require 15 different amplifiers, each one with its own reference voltage and its inverting input. The output of all amplifiers must be coded into four-line output codes. Since the encoder is asynchronous, it is better to use Gray code. The encoder also requires feedback logic, for only the highest activated difference amplifier must energize the matrix.
It would be desirable if there were provided an analog-to-digital conversion technique that has a high speed sampling rate, but minimize the logic units required.